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AR# 42412

13.1 EDK, XPS_IIC - The driver example code does not flush the Tx FIFO when the protocol is abnormally terminated

Description

According to the xps_iic data sheet, the Tx_FIFO needs to be cleared any time the protocol is abnormally terminated. However, the example code does not follow this recommendation. As a result, there is a possibility that the Tx_FIFO can get corrupted causing illegal IIC transactions on the bus.

Solution

The following changes are requiredin EepromWriteByte function in the example code to reset the FIFO so as to avoid such a situation.

For the pre-send ACK polling:
/*
* Set the address register to the specified address by writing
* the address to the device, this must be tried until it succeeds
* because a previous write to the device could be pending and it
* will not ack until that write is complete.
*/
do {
SentByteCount = XIic_Send(IIC_BASE_ADDRESS,EepromIicAddr, (u8 *)&Address, sizeof(Address),XIIC_STOP);
if (SentByteCount != sizeof(Address)) {
//send aborted. reset Tx_FIFO
XIic_WriteReg(IIC_BASE_ADDRESS, XIIC_CR_REG_OFFSET,XIIC_CR_TX_FIFO_RESET_MASK);
XIic_WriteReg(IIC_BASE_ADDRESS, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
//poll_cnt0++;
}

} while (SentByteCount != sizeof(Address));


For the post-send ACK polling
/*
* Wait for the write to be complete by trying to do a write and
* the device will not ack if the write is still active.
*/
do {
AckByteCount = XIic_Send(IIC_BASE_ADDRESS, EepromIicAddr, (u8 *)&Address, sizeof(Address), XIIC_STOP);
if (AckByteCount != sizeof(Address)) {
//send aborted. reset Tx_FIFO
XIic_WriteReg(IIC_BASE_ADDRESS, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK);
XIic_WriteReg(IIC_BASE_ADDRESS, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK);
//poll_cnt1++;
}

} while (AckByteCount != sizeof(Address));

AR# 42412
Date Created 06/30/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
IP
  • XPS IIC Bus Interface