^
Advanced Search

AR# 42454 Spartan-6 FPGA Integrated Block for PCI Express - CORE Generator GUI shows a value of 0 for bit 15 of the Device Capabilities Register

Description

Version Found: v2.1
Version Resolved and other Known Issues: See (Xilinx Answer 45702).

The CORE Generator GUI shows that the Role-Based Error reporting bit or bit 15 of the Device Capabilities Register is set to 0. However, if this bit is read back from the core it is set.

Solution

The CORE Generator display value is incorrect and this bit is actually set to 1.

Revision History
01/18/2012 - Updated; added reference to 45072
07/06/2011 - Initial Release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42569 Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.3 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
45702 Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions N/A N/A

Actions

AR# 42454
Date Created 06/10/2011
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LXT
Tools
  • ISE Design Suite - 13.2
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )
Feed Back