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AR# 42470

PlanAhead - Interactive DRC Prevents Correction of Pin Placement Error in Package View


The following sequence of events prevents the DRC from correcting pin placement errors:

1. Assign pins to a bank and then set an I/O standard, for example, lvdci_25, which requires VRP/VRN sites.
2. Run DRC. DRC flags errors that these pins are occupied.
3. Go to the package view and try to drag and drop the offending I/Os to another site, and DRC prevents this.


The issue here is that when the drag-and-drop placement is checking the legality of the placement, it returns false if there is a VRN/VRP/VREF conflict in the bank, regardless of whether that conflict is caused by the placement of the port the user is moving.

To work around this issue, select the I/O in VRN/VRP, RMB Unplace, and do the same for the other site (if applicable). Next, go back to the I/O Ports tab, and drag and drop the I/Os to valid sites.
AR# 42470
Date Created 07/11/2011
Last Updated 02/29/2012
Status Active
Type Known Issues
  • Spartan/XL
  • Spartan-3
  • Spartan-3 XA
  • More
  • Spartan-3A
  • Spartan-3A DSP
  • Spartan-3AN
  • Spartan-3E
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
  • Virtex QPro/R
  • Virtex-4 FX
  • Virtex-4 LX
  • Virtex-4 QPro/R
  • Virtex-4 SX
  • Virtex-4Q
  • Virtex-4QV
  • Virtex-5 FXT
  • Virtex-5 LX
  • Virtex-5 LXT
  • Virtex-5 SXT
  • Virtex-5 TXT
  • Virtex-5Q
  • Virtex-5QV
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-7
  • Virtex-7 HT
  • Less
  • PlanAhead - 13.2