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AR# 42543

7 Series Configuration - ConfigFallback: Enable|Disable default settings


By default, Fallback is disabled for 7 series devices. This is for single image flows specifically. For Multiboot flows, ConfigFallback is Enabled by default. The reason for this is that when Fallback is enabled, the Status Register is cleared after a failed configuration attempt affecting debug as described in (Xilinx Answer 42544).


ConfigFallback disabled by default can cause issues for Multiboot designs. When Fallback is disabled, if you encounter an error in an attempt to IPROG Multiboot to a new image, Fallback does not occur. This can lead to a looping effect where multiple IPROG Multiboots are attempted and the flash device loops around to address 0x0, reloading the golden each time. The FPGA continues reading the flash, wraps around, and starts over from the first image.

For both BPI and SPI, the flash interface is not terminated.

For BPI, the fcs_b/foe_b are low and address continues to increment.

For SPI, the fcs_b is low after the read command was initially sent. So, the flash continues to be in read mode and most SPI flash devices internally wrap around.

When generating a Multiboot design, Bitgen automatically changes the default of configFallback to Enable. This change is as of 13.3.

AR# 42543
Date Created 06/15/2011
Last Updated 01/23/2013
Status Active
Type General Article
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2