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AR# 42551

Aurora 8b/10b - Known Issues and Answer Records List

Description

The following answer records cover current known issues as well as commonly asked questions related to Aurora 8b/10b.

NOTE: This answer record is part of the Xilinx Aurora Solution Center (Xilinx Answer 21263)

The Xilinx Aurora Solution Center is available to address all questions related to Aurora.

Solution

(Xilinx Answer 54367)  LogiCORE IP Aurora 8B10B - Release Notes and Known Issues for Vivado 2013.1 and later tool versions

Known Issues:

(Xilinx Answer 46879) Aurora 8B/10B v7.1/v5.3 - The core resets every 4520 USER_CLK cycles with RXNOTINTABLE errors

(Xilinx Answer 52493) LogiCORE IP Aurora 8B10B v8.3, ISE 14.3 - CRC failure in timing simulation using ISE generated Place and Route netlist
(Xilinx Answer 52492) LogiCORE IP Aurora 8B10B v8.3 - ISE 14.3 - Timing simulation of the IP example design fails when using ISE generated Place and Route netlist
(Xilinx Answer 42187) Spartan-6 GTP Aurora 8b/10b - Line rates extended
(Xilinx Answer 41149) Spartan-6 GTP Aurora 8b/10b v6.1 - Channel bonding in slave not assigned correctly in same tile as master
(Xilinx Answer 40355) Aurora 8b/10b - FRAME_ERR stays high after reconnecting cable
(Xilinx Answer 39645) Virtex-6 GTX Aurora 8B/10B/Aurora 64b/66b - Auto Link recovery during hot-plug
(Xilinx Answer 38956) Aurora 8B10B v5.2 and v6.1 - Clock correction is disabled in the example design
(Xilinx Answer 38492) Aurora 8b/10b 64b/66b - "ERROR:PhysDesignRules:2270 when forwarding REFCLK over unused tiles"
(Xilinx Answer 36328) Aurora 8b/10b 64b/66b - REFCLK error occurs when creating core in different OS than the XCO file
(Xilinx Answer 35448) Getting Started Guides replaced by new User Guides
(Xilinx Answer 34208) Spartan-6 Aurora 8b/10b - Clock correction sequence not recognized in GTP1 in tile
(Xilinx Answer 33768) Aurora 8B/10B v4.2 - Channel bonding fails if it is synthesized by Synplify Pro/Premier
(Xilinx Answer 33284) Aurora 8B/10B v4.2 - Data alignment can be to either byte 0 or 2 for cores targeting GTX in 4-byte mode

Release Notes:

(Xilinx Answer 32745) Aurora 8B/10B v4.2 - Release Notes and Known Issues for ISE Design Suite 11.2
(Xilinx Answer 35372) Aurora 8B/10B v5.1 - Release Notes and Known Issues for ISE Design Suite 11.4
(Xilinx Answer 42585) Aurora 8B/10B v5.2 - Release Notes and Known Issues for ISE Design Suite 12.2
(Xilinx Answer 38409) Aurora 8B/10B v6.1 - Release Notes and Known Issues for ISE Design Suite 12.3 (AXI4-stream)
(Xilinx Answer 42586) Aurora 8B/10B v6.2 - Release Notes and Known Issues for ISE Design Suite 13.1 (AXI4-stream)
(Xilinx Answer 44596) Aurora 8B/10B v7.1 - Release Notes and Known Issues for ISE Design Suite 13.3 (AXI4-stream)
(Xilinx Answer 45672) Aurora 8B/10B v5.3 - Release Notes and Known Issues for ISE Design Suite 13.4
(Xilinx Answer 47702) LogiCORE IP Aurora 8B10B v8.1 (AXI4-stream) (ISE 14.1/Vivado 2012.1) - Release Notes and Known Issues
(Xilinx Answer 52311) LogiCORE IP Aurora 8B10B v8.3 (AXI4-stream) (ISE 14.3/Vivado 2012.3), v8.3Rev1 (Vivado 2012.4) - Release Notes and Known Issues

AR# 42551
Date Created 06/15/2011
Last Updated 09/12/2014
Status Active
Type Known Issues
IP
  • Aurora 8B/10B