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AR# 42565 Vivado HLS - Can the internal FIFO depth be forced with set_directive_interface -depth option?

Setting the following directives does not update the output of the Verilog or VHDL parameter of INTERNAL_WFIFO_DEPTH:

set_directive_interface -mode ap_bus "foo" out -depth 8

Can the internal FIFO depth be forced with set_directive_interface -depth option?
The internalFIFO depth (INTERNAL_WFIFO_DEPTH) and MEM_LATENCY generics are maintained by the Vivado HLS synthesis engine. Therefore,users cannot configure them with directives and should not change the value manually. The "-depth" option for the directive is only used by the C-RTL mixed simulation. It controls the depth of the FIFO between C Testbench and the RTL. This option is not used in RTL implementation.

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47431 Xilinx Vivado HLS Solution Center - Design Assistant N/A N/A
AR# 42565
Date Created 01/10/2012
Last Updated 02/17/2013
Status Active
Type General Article
Tools
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