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AR# 42573

SPI-4.2 v10.5 and earlier - Timing errors seen when performance is 1.2 Gpbs and the TSCLK is on global clocking


When targeting a Virtex-5 device, timing errors are seen when performance is 1.2 Gbps and the TSCLK is on global clocking. 


This is due to a component limit switch failure on the TSClk DCM.   This issue occurs because when source core TSClk is configured to use a DCM and performance is at 1.2 Gpbs, the DCM attributes DLL and DFS_FREQUENCY_MODE are set to LOW instead of HIGH.  The workaround is to set these attributes via UCF. Example:

INST "core_pl4_src_top0/U0/clk0/tsd" DLL_FREQUENCY_MODE = "HIGH";
INST "core_pl4_src_top0/U0/clk0/tsd" DFS_FREQUENCY_MODE = "HIGH";

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42572 SPI-4.2 v10.5 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A
AR# 42573
Date Created 06/28/2011
Last Updated 05/23/2014
Status Archive
Type General Article
  • SPI-4 Phase 2 Interface Solutions