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AR# 42586 Aurora 8B/10B v6.2 - Release Notes and Known Issues for ISE Design Suite 13.1

Description

This Answer Record contains the Release Notes for the Aurora 8B/10B v6.2 Core, released in ISE 13.1, and includes the following:
  • New Features
  • Bug Fixes
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:

http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf.

Solution

New Features

  • ISE 13.1 software support
  • ISIM simulator support
  • PlanAhead support
  • projNav flow support
Supported Devices
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Spartan-6 XC LXT
  • Spartan-6 XA
  • Spartan-6 XQ LXT

Resolved Issues

  • Change the limit to achieve lower VCO frequency for Virtex-6 GTX designs
    CR number 584627
  • All UFC signals enabled by default for RX simplex and TX simplex in IP symbol
    CR number 584592
  • Aurora - S6 - GTP Implementation incorrect for channel bonding
    CR number 582596
  • Aurora v5.2 and 6.1 - Clock correction disabled in the example design after all lanes are up
    CR number 581815
  • Aurora 8b/10b v5.2 - simplex sideband signal extend process has redundancy
    CR number 577182
  • Defeature DIVCLK_DIVIDE = 3 or 4 for Virtex-6 MMCM when MMCM CLKIN_FREQ > 315Mhz
    CR number 575944
  • Timing constraint does not meet for TS_GTXQ3_LEFT_I
    CR number 572684
  • Extend the line rate support from 3.125 Gbps to 3.2 Gbps in Spartan-6 for -3 and -4 speedgrade
    CR number 572326
  • Reverse the VIO port mapping in VHDL design
    CR number 568806
  • Add ERR_COUNT constraints in UCF files
    CR number 532277

Known Issues

GT wrapper compatibility module name:

Change the copied wizard generated wrapper module name to all uppercase before using it with Aurora core. This is applicable for Verilog based designs only. For more detailed information, refer to UG766 Appendix C.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43347 Kintex-7 FPGA Initial Engineering Sample (ES) - Known Issues Master Answer Record N/A N/A

Actions

AR# 42586
Date Created 06/14/2011
Last Updated 03/01/2013
Status Active
Type Release Notes
IP
  • Aurora 8B/10B
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