The new DRC check is valid. The MMCM and the PLL have some restrictions that must be adhered to:
For phase shift,the allowable phase-shift values are determined based on the MMCM configuration settings.The granularity of the CLKOUT phase-shift value can be calculated as 45/CLKOUT_DIVIDE value.
The static phase-shift (SPS) resolution in time units is defined as:
SPS=1/8/Fvco period or D/M/Fin period
Since the VCO can provide eight phase shifted clocks at 45 each; always providing possible settings for 0, 45, 90, 135, 180, 225, 270, and 315 of phase shift. The higher the VCO frequency is, the smaller the phase-shift resolution. Since the VCO has a distinct operating range, it is possible to bound the phase-shift resolution using from 1/8/Fvcomin to 1/8Fvcomax period.
For more information, please refer to 7 Series FPGAs Clocking Resources User Guide (UG472).