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AR# 42600

13.2 Map - ERROR:PhysDesignRules - Invalid CLKOUT[*]_PHASE value (*.*) for PLL_ADV


In ISE 13.2, Map reports thefollowing error:

ERROR:PhysDesignRules - Invalid CLKOUT3_PHASE value (3.0) for PLL_ADV (block
u_ddr3_top/u_mig_7series_80b_64b/u_ddr3_infrastructure/plle2_i). It should be a multiple of [45 / CLKOUT3_DIVIDE] =
[45 / 8] = 5.625000.
ERROR:Pack:1642 - Errors in physical DRC.

However, ISE 13.1 software did not report this error.


The new DRC check is valid. The MMCM and the PLL have some restrictions that must be adhered to:

For phase shift,the allowable phase-shift values are determined based on the MMCM configuration settings.The granularity of the CLKOUT phase-shift value can be calculated as 45/CLKOUT_DIVIDE value.

The static phase-shift (SPS) resolution in time units is defined as:

SPS=1/8/Fvco period or D/M/Fin period

Since the VCO can provide eight phase shifted clocks at 45 each; always providing possible settings for 0, 45, 90, 135, 180, 225, 270, and 315 of phase shift. The higher the VCO frequency is, the smaller the phase-shift resolution. Since the VCO has a distinct operating range, it is possible to bound the phase-shift resolution using from 1/8/Fvcomin to 1/8Fvcomax period.

For more information, please refer to 7 Series FPGAs Clocking Resources User Guide (UG472).

AR# 42600
Date 12/15/2012
Status Active
Type General Article
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
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