UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42604

FIFO Generator v8.2 : Independent Clock Built-in FIFO Write and Read Clock Frequency Setting in Coregen GUI

Description

The Independent Clock Built-in FIFO Write and Read Clock Frequency Setting in the CORE Generator GUI does not allow users to set a frequency above 100 MHz. The auto upgrade feature will not work for frequency settings above 100 MHz for core versions 8.1 and earlier.

Solution

To work around this issue, lowering the write and read frequency with the same ratio below the 100 MHz frequency is recommended. The issue is scheduled to be fixed in the ISE 13.3 software release.

For example, if the required write frequency is 150 MHz and read frequency is 200 MHz, then the ratio here is 3:4, and you can lower the write and read frequency to 75 MHz and 100 MHz (or 60/80, 30/40, etc).

The issue is scheduled to be fixed in the ISE 13.3 software release.
AR# 42604
Date Created 06/14/2011
Last Updated 06/21/2011
Status Archive
Type General Article
IP
  • FIFO Generator