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AR# 42614

SPI-4.2 v11.2 (AXI) - In a Timing Simulation, IDELAYE2 Output DATAOUT is "X" from the Start of Simulation


Sometimes, when targeting the Virtex-7 or Kintex-7 devices during a timing simulation with the SPI-4.2 core, the IDELAYE2 output DATAOUT is "X" from the start of the simulation.


This failure has a very low occurrence and is currently being investigated.  Please open a Xilinx technical support webcase if the issue is encountered. 

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42612 SPI-4.2 v11.2 (AXI) - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A
AR# 42614
Date Created 06/27/2011
Last Updated 05/26/2014
Status Archive
Type General Article
  • SPI-4 Phase 2 Interface Solutions