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AR# 42624

Aurora 64B/66B v4.2 - Release Notes and Known Issues for ISE Design Suite 13.1

Description

This Answer Record contains the Release Notes for the Aurora 64B/66B v4.2 Core, released in ISE DesignSuite 13.1, and includes the following:
  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf

Solution

New Features

  • ISE 13.1 software support
  • Virtex-6 HXT/GTH VHDL support

Supported Devices

  • Virtex-6 XC LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Virtex-5 XC TXT/FXT
  • Virtex-5 XQ FXT

Resolved Issues

  • C_REFCLK_FREQUENCY value error between Linux and Windows OS
    CR# 575821
  • Data loss due to misalignment of RXData from CC logic
    CR# 566873
  • Virtex-6 GTX Transceiver - MMCM fails to lock and TX/RXRESETDONE fails to assert
    CR# 571155
  • Virtex-6 MMCM does not lock
    CR# 571149
  • GTX_TX_CLK_SOURCE should point to TXPLL for Simplex TX designs
    CR# 570887
  • TXPLLKDET is not high in Virtex-6 GT Wrapper
    CR# 573476

Known Issues

  • Virtex-6 HXT/GTH max lanes supported is 8 lanes.
  • Virtex-6 HXT/GTH selection of quads should be consecutive.
  • There cannot be an unused quad between two used quads.
  • Virtex-6 HXT/GTH solutions are pending for hardware validation.
  • Virtex-5 FXT/TXT DRC error when GTP/GTX reference clock sourced or routed through unused DUAL; see (Xilinx Answer 33473).
AR# 42624
Date Created 06/15/2011
Last Updated 05/19/2012
Status Active
Type Release Notes
IP
  • Aurora 64B/66B