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AR# 42626 7 Series Integrated Wrapper for LogiCORE CPRI - Port Changes in GTXE2_Common Wrapper in ISE Design Suite 13.2

Description

Customers using the13.1 ISE Design Suite software version should be aware that the port list in 7 Series FPGAs Transceivers Wizard v1.4 released with ISE 13.2 has been modified. As a result, users need to update their instantiations to account for these port changes.

Solution

To manage this issue, there are two changes required to the GTXE2 modules.

GTXE2_COMMON Module

Note: These changes only apply to cores that select 9.830 Gbps.

1. Go to the v7_gtwizard.vhd file in the example_design/gtx_and_clocks/gtx directory.

2. Change the following lines in the v7_gtwizard.vhd file:

Change:

BGBYPASS=> tied_to_ground_i,
BGMONITOREN=> tied_to_ground_i,

To:

BGBYPASSB => tied_to_vcc_i,
BGMONITORENB=> tied_to_vcc_i,

GTXE2_CHANNEL Module

Note: These changes apply to cores that select any line rate.

1. Go to the v7_gtwizard_gt.vhd file in the example_design/gtx_and_clocks/gtx directory.

2. Change the following lines in the v7_gtwizard_gt.vhd file:

Change:

'CPLL_RXOUT_DIV'

To:

'RXOUT_DIV'

Change:

'CPLL_TXOUT_DIV'

To:

'TXOUT_DIV'

For Release Notes and Known Issues for the LogiCORE CPRI, please see (Xilinx Answer 36969).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
36969 LogiCORE IP CPRI - Release Notes and Known Issues N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
42615 Design Advisory for 7 Series FPGA Transceivers - GTX Port Name Changes in ISE 13.2 Software N/A N/A

Actions

AR# 42626
Date Created 06/24/2011
Last Updated 08/21/2012
Status Active
Type Design Advisory
IP
  • CPRI
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