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AR# 42662

7 Series GTX Transceivers - TX and RX Latency Values


This answer record provides the TX and RX latency values for the 7 series FPGA GTX Transceiver. The tables will be added to the 7 Series FPGAs GTX/GTH Transceivers User Guide(UG476).



1. The minimum and maximum are theoretical. These configurations might not map to any protocol. USRCLK and USRCLK2 phases are assumed to be matching according to the user guide.

2. There is a typo in this TX latency table. The latency is shown in terms of RXUSRCLK cycle, but it is meant to be TXUSRCLK.

Note: Please note that RXDDIEN must be 1 to ensure predictable, fixed latency when using RX buffer bypass.

Note 1: The latency through the TX fabric interface will depend on one's precise definition of latency. The entries in the tables above are accurate if latency is defined as the time from the clock edge that puts data on TXDATA to the clock edge that clocks the first part of that data out of the fabric interface (into the internal PCS), neglecting clock insertion time from the fabric into the GT.

Note 2: When coming out of reset, the latency through the elastic buffer is:                                     
2 RXUSRCLK cycles             
+ CLK_COR_MIN_LAT byte times               
+/-  0.5 RXUSRCLK cycles     

Note that this formula is only valid at the time the buffer comes out of reset. For general operation please use the latency table.

AR# 42662
Date Created 06/16/2011
Last Updated 07/15/2013
Status Active
Type AFE Reference Design
  • Artix-7
  • Kintex-7
  • Virtex-7