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AR# 42672

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.1, 7 Series Transceiver Wrapper - GTX Port Name Changes in ISE 13.2 Software

Description

Customers using the Ethernet 1000BASE-X PCS/PMA or SGMII v11.1 core (released in ISE13.1 software) should be aware that the port list in 7 Series FPGAs Transceivers has changed (released in the ISE 13.2 software). For simulation or implementation in the 13.2 software, users need to update their instantiations to account for these port changes. For more information on the change, see (Xilinx Answer 42615).

Solution

To work aroundthis issue, you must change the ports of GTXE2 module instantiation.

GTXE2_CHANNEL Instantiation

In the \example_design\transceiver\gtxwizard_gt.v/vhd file:

Change:

'CPLL_RXOUT_DIV'

To:

'RXOUT_DIV'

and...

Change:

'CPLL_TXOUT_DIV'
To:

'TXOUT_DIV'

Linked Answer Records

Master Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
42615 Design Advisory for 7 Series FPGA Transceivers - GTX Port Name Changes in ISE 13.2 Software N/A N/A
AR# 42672
Date Created 06/29/2011
Last Updated 12/15/2012
Status Active
Type General Article
IP
  • Ethernet 1000BASE-X PCS/PMA or SGMII