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AR# 42682

Design Advisory for Virtex-6, 13.x/14.x iMPACT - eFUSE key programming incorrect when target FPGA is not the only device in the JTAG chain

Description

iMPACT v13.3 does not permit programming Virtex-6 FPGA eFUSE values in JTAG chains of more than one device. The following message appears in the console and log file:

 "WARNING:iMPACT - '2': iMPACT software is unable to program the V6 eFUSE values if there is more than 1 device in the JTAG chain. For more information, consult (Xilinx Answer 42682)."

Solution

There is an issue in programming that prevents the key from being programmed properly in this scenario (see additional information provided for the 13.2 case below).

For version 13.2 and earlier, when programming a Virtex-6 FPGA eFuse register in a JTAG chain of more than one device, the 256 AES key programmed into the FPGA does not match the intended value. This failure is captured and noted at program time with a message similar to the following:

'2': Verifying FUSE_KEY register with high margin...

'2': Data to be programmed for FUSE_KEY = 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

'2': Actual programmed data read from FUSE_KEY = 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

'2': High Margin Verify Failed.

There are three possible work-arounds for this issue:

  • Isolate the FPGA as the only device in the JTAG chain. The key is programmed as expected in this scenario.
  • In 13.2 and previous versions, do not disable eFUSE programming and the following workaround is applicable:

    While the key in the device does not match the value in the key file (design.nky), the encryption functionality in the FPGA still works. Perform a readback of the eFUSE key (or use the read back value shown in the iMPACT log) to determine the value programmed into the device. Reformat the key value as 64 hex digits, replace the value in the ".nky" file and save as a new ".nky" file. Then, use this new ".nky" file by specifying it as the encryption key in BitGen, and regenerate the bitstream. This new bitstream should be able to configure the FPGA because the key matches the value stored in the eFUSE rather than the original key used for programming.

    Note: It is necessary to have two ".nky" files; one for programming the eFUSE, and the other for generating FPGA bitstreams. At programming time, this should work provided that the target FPGA is in the same position in the JTAG chain. If the FPGA might be in different positions in the JTAG chain, this workaround will require separate ".nky" files for each position.
  • Xilinx is able to anticipate the key corruption, and therefore, is able to assist with the generation of an "intermediate" key value which allows the original key value used for bitstream generation to be ultimately programmed into the FPGA. For this solution, please contact Technical Support for more information.

This issue is targeted for a fix in 14.5 iMPACT. A scripted fix is available, and can be obtained through Technical Support. For access to this fix, open a WebCase and reference (Xilinx Answer 42682).

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47890 14.x iMPACT - Known Issues for the iMPACT 14.x tools N/A N/A
40503 13.x iMPACT - Known Issues for the iMPACT 13.x Software N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
34565 Design Advisory Master Answer Record for Virtex-6 FPGA N/A N/A
40503 13.x iMPACT - Known Issues for the iMPACT 13.x Software N/A N/A
AR# 42682
Date Created 06/30/2011
Last Updated 03/27/2013
Status Active
Type Design Advisory
Devices
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
  • More
  • Virtex-6 LXT
  • Virtex-6 SXT
  • Virtex-6Q
  • Virtex-6QL
  • Less
Tools
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2
  • ISE Design Suite - 13.3
  • More
  • ISE Design Suite - 13.4
  • ISE Design Suite - 14.1
  • Less