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AR# 42690

13.1 Timing - Block RAM in a Spartan-6 device in SDP mode includes invalid timing path

Description

In SDP mode on a Spartan-6 device block RAM, both input ports are clocked on CLKA and both output ports are clocked on CLKB. However, TRCE reports timing paths from CLKA (write clock) on the output ports to the other synchronous components.

Solution

The issue is scheduled to be fixed in O.61xd.

To work around this issue, add constraints to ignore the path which should not be analyzed.

For example:

NET "clk_wr" TNM = RAMS "BRAM_WR";
TIMESPEC TS_BRAM_WR_FF = FROM "BRAM_WR" TO "FFS" TIG;

AR# 42690
Date Created 04/27/2012
Last Updated 12/15/2012
Status Active
Type General Article
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
Tools
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • More
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • Less