We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42694

13.2 PlanAhead - PlanAhead is not ordering source files correctly in the synthesis PRJ file


Using "Auto-Reorder Source Files" in PlanAhead tool does notwork properlyif the design uses a mixture of direct instantiation and relative work libraries as below:

vhdl theor "./theor/gate.vhd"
vhdl theand "./theand/box.vhd"
vhdl work "./gate.vhd"
vhdl theand "./theand/gate.vhd"
vhdl theor "./theor/box.vhd"
vhdl work "./top.vhd"


If you have this case,manuallyreordering source files is a workaround.

This issuewill be fixed in PlanAhead tool 13.3.

AR# 42694
Date Created 07/11/2011
Last Updated 12/15/2012
Status Active
Type General Article