This Release Note is for the Distributed Memory Generator Core v6.2 released in ISE Design Suite 13.2, and contains the following information:
For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:
For the most recent updates to the IP installation instructions for this core, please go to:
For system requirements:
This file contains release notes for the Xilinx LogiCORE IP Distributed Memory Generator Core v6.2 solution. For the latest core updates, see the product page at:
New Features in v6.2
Bug Fixes in v6.2
The following issue is resolved in v6.2:
When a large Distributed Memory Generator IP is generated, the CORE Generator runs out of memory and fails to generate.
Known Issues in v6.2
To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.