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AR# 42716

LogiCORE Distributed Memory Generator v6.2 - Release Notes and Known Issues for ISE Design Suite 13.2


This Release Note is for the Distributed Memory Generator Core v6.2 released in ISE Design Suite 13.2, and contains the following information: 

  • General Information 
  • New Features 
  • Bug Fixes 
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at:


General Information

For the most recent updates to the IP installation instructions for this core, please go to:

For system requirements:

This file contains release notes for the Xilinx LogiCORE IP Distributed Memory Generator Core v6.2 solution. For the latest core updates, see the product page at: 

New Features in v6.2

  • ISE 13.2 software support
  • Kintex-7L, Virtex-7L, Artix-7 and Zynq device support

Bug Fixes in v6.2

The following issue is resolved in v6.2:

When a large Distributed Memory Generator IP is generated, the CORE Generator runs out of memory and fails to generate.

Known Issues in v6.2

Technical Support

To obtain technical support, create a WebCase at www.xilinx.com/support. Questions are routed to a team with expertise using this product.

Xilinx provides technical support for use of this product when used according to the guidelines described in the core documentation and cannot guarantee timing, functionality, or support of this product for designs that do not follow specified guidelines.

AR# 42716
Date 11/10/2014
Status Archive
Type Release Notes
  • ISE Design Suite - 13.2
  • ISE - 10.1
  • ISE Design Suite - 11.1
  • More
  • ISE Design Suite - 11.2
  • ISE Design Suite - 11.3
  • ISE Design Suite - 11.4
  • ISE Design Suite - 11.5
  • ISE Design Suite - 12.1
  • ISE Design Suite - 12.2
  • ISE Design Suite - 12.3
  • ISE Design Suite - 12.4
  • ISE Design Suite - 13
  • ISE Design Suite - 13.1
  • Less
  • Distributed Memory Generator
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