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AR# 42730 MIG 7 Series v1.1-v1.2 QDRII+ - %CLK_STABLE is passed to CLK_STABLE parameter in .veo instantiation file

Description

Why is the CLK_STABLE parameter in the Verilog .VEO instantiation file set to %CLK_STABLE?

Solution

This is a known issue with the MIG v1.1-v1.2 QDRII+ *.VEO instantiation file as the CLK_STABLE parameter should be set to the number of cycles to wait until the echo clocks are stable. This value is dependent on the memory vendor's data sheet but is set to 2048 by default.

This will be fixed in the ISE 13.3 software release but can be worked around by setting the value of the CLK_STABLE parameter manually in the .VEO instantiation file.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
41227 MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A
40050 MIG 7 Series v1.1 - Release Notes and Known Issues for ISE Design Suite 13.1 N/A N/A
41227 MIG 7 Series v1.2 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A

Actions

AR# 42730
Date Created 06/20/2011
Last Updated 05/20/2012
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG
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