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AR# 42749

Spartan-6 FPGA Integrated Block for PCI Express - Some Bits of m_axis_rx_tuser Not Defined in User Guide

Description

Version Found: v2.1
Version Resolved and other Known Issues: See (Xilinx Answer 45702).

Bits 16, 15, and 0 of the m_axis_rx_tuser bus are not defined in the Spartan-6 FPGA Integrated endpoint block for PCI Express pre-Production User Guide, (UG672).

Solution

These bits are reserved; therefore, they arenot used.

Release History
01/18/2012 - Updated; added reference to 45072
07/06/2011 - Initial Release

Note: "Version Found" refers to the version the problem was first discovered. The problem might also exist in earlier versions, but no specific testing has been performed to verify earlier versions.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42569 Spartan-6 FPGA Integrated Block Wrapper for PCI Express (AXI) - Resolved issues in v2.3 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
45702 Spartan-6 FPGA Integrated Block for PCI Express - Release Notes and Known Issues for all AXI Interface versions N/A N/A
AR# 42749
Date Created 06/21/2011
Last Updated 05/20/2012
Status Active
Type Release Notes
Devices
  • Spartan-6 LXT
IP
  • Spartan-6 FPGA Integrated Endpoint Block for PCI Express ( PCIe )