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AR# 42796

Spartan-6 - IODELAY2 How long does it take for BUSY to assert/de-assert?


In the Spartan-6 IODELAY2, the BUSY signal goes high when using the variable delay mode and incrementing or decrementing the delay.How long does it take for BUSY to assert, and can the de-asserting of BUSY be used to ensure data is valid?


When incrementing or decrementing the delay in the IODELAY2, the BUSY signal will assert to indicate that the DATAOUT is not valid and this will occur within a few CLK cycles of the CE pin being asserted.

To ensure that the data being sampled at the IODELAY2 is valid, the user should monitor the BUSY signal and wait for BUSY to de-assert. Monitoring BUSY is the best way to determine valid output data, because waiting for a timed increment to pass can be unreliable due to number of variable conditions.

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
46791 Spartan-6 FPGA Design Assistant - Troubleshoot Common Fabric Problems N/A N/A
AR# 42796
Date Created 08/03/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q