When incrementing or decrementing the delay in the IODELAY2, the BUSY signal will assert to indicate that the DATAOUT is not valid and this will occur within a few CLK cycles of the CE pin being asserted.
To ensure that the data being sampled at the IODELAY2 is valid, the user should monitor the BUSY signal and wait for BUSY to de-assert. Monitoring BUSY is the best way to determine valid output data, because waiting for a timed increment to pass can be unreliable due to number of variable conditions.
| Answer Number | Answer Title | Version Found | Version Resolved |
|---|---|---|---|
| 46791 | Spartan-6 FPGA Design Assistant - Troubleshoot Common Fabric Problems | N/A | N/A |