To support selfrefresh with suspend correctly, the MIG Veriloginfrastructure.v moduleneeds to be modified to add a clock enable to the BUFG for themcb_drp_clk clock signal.
The original infrastructure.v code:
The required infrastructure.v code:
This issue is fixed in MIG 3.9 included in the13.3 ISE Design Suite.
NOTE: The addition of the CE port does not work when targeting the "CES" SP601 boards. When you target this revision of the board with the MIG 3.9 or later code, make sure you replace the original BUFG instantiation listed above in the infrastructure.v module.