UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42802

MIG 3.8 Spartan-6 MCB - Selfrefresh with Suspend Mode Support Requires BUFGCE in Infrastructure.v Module

Description

There have been several changes to the 13.2 ISE Design Suiteto support selfrefresh with suspend for Spartan-6 MCB designs.An issue was observed in that the BUFG for the mcb_drp_clk in the infrastructure.v module required a Clock Enable controlled by the lock signal from the PLL to support selfrefresh with suspend correctly. For the 13.2 ISE Design Suite, this has not been implemented for Verilog designs.This issue does not exist for VHDL designs.To work around this issue, please see the details below.

Solution

To support selfrefresh with suspend correctly, the MIG Veriloginfrastructure.v moduleneeds to be modified to add a clock enable to the BUFG for themcb_drp_clk clock signal.

The original infrastructure.v code:

BUFG U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in)
);

The required infrastructure.v code:

BUFGCE U_BUFG_CLK1
(
.O (mcb_drp_clk),
.I (mcb_drp_clk_bufg_in),
.CE (locked)
);

This issue is fixed in MIG 3.9 included in the13.3 ISE Design Suite.

NOTE: The addition of the CE port does not work when targeting the "CES" SP601 boards. When you target this revision of the board with the MIG 3.9 or later code, make sure you replace the original BUFG instantiation listed above in the infrastructure.v module.

AR# 42802
Date Created 07/05/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
Devices
  • Spartan-6 LX
  • Spartan-6 LXT
  • Spartan-6Q
IP
  • MIG