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AR# 42804

Aurora 64B/66B v6.1 - Release Notes and Known Issues for ISE Design Suite 13.2


This Answer Record contains the Release Notes for the Aurora 64B/66B v6.1 Core, released in ISE Design Suite 13.2, and includes the following:

  • New Features
  • Supported Devices
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide at: http://www.xilinx.com/support/documentation/ip_documentation/xtp025.pdf.


New Features

  • ISE 13.2 software support
  • Kintex-7/Virtex-7 support added
  • 12 lane support for Virtex-6 - GTH devices
  • PlanAhead flow support
  • ISIM/NCSIM simulator support
  • Synplify support

Supported Devices

  • Virtex-6 XC LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Virtex-7
  • Virtex-7 XT (7vx485t)
  • Virtex-7 -2L
  • Kintex-7
  • Kintex-7 -2L

Resolved Issues

  • 2 cycles of pause after every 32 frames
    Description: User interface is paused for 2 cycles after 32 cycles to accomodate stuffing of 66-bits of data
    Version fixed: v6.1
    CR# 568960
  • PMA_CDR_SCAN value - not adjusted properly
    Description: PMA_CDR_SCAN value is not set in-line with Transceiver wizard value
    Version fixed: v6.1
    CR# 589092
  • VHDL designs fail on ISIM
    Description: ISIM scripts error out when a VHDL design is compiled
    Version fixed: v6.1
    CR# 595129
  • Updates to GTH attributes
    Description: Updates for Production HXT, attributes, and initialization sequences
    Version fixed: v6.1
    CR# 595952
    AR# 40902
  • Missing EOF during datavalid from Gearbox
    Description: EOF missed when CC coincides with datavalid from the Gearbox
    Version fixed: v6.1
    CR# 603961

Known Issues

The following items are known issues for v6.1 of this core at time of release:

  • Virtex-7/Kintex-7 supports simulation only
    Description: For Virtex-7/Kintex-7 the core supports simulation only
  • Virtex-6 HXT/GTH selection of quads should be consecutive
    Description: In Virtex-6 HXT/GTH, for line rates >9.8G the quad selection should be consecutive. There cannot be a unused quad between two used quads
  • Virtex-6 HXT/GTH solutions are pending for hardware validation
    Description: Virtex-6 GTH designs are not validated on hardware
  • Virtex-6 HXT/GTH ES/PS attribiute settings
    Description: Refer to Aurora 64B66B v5.1 for ES settings for GTH transceivers
    Refer to Aurora 64B66B v6.1 for PS settings for GTH transceivers
  • QVirtex-6L devices are not supported
    Description: Core is not enabled when QVirtex6L devices are selected
  • Core does not generate for 0.5G line rate for Virtex-7/Kintex-7 devices
    Description: When Virtex-7/Kintex-7 device is targeted for 0.5G as line rate, the core errors on generation

Linked Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43347 Kintex-7 FPGA Initial Engineering Sample (ES) - Known Issues Master Answer Record N/A N/A
AR# 42804
Date Created 07/12/2011
Last Updated 05/19/2012
Status Active
Type Release Notes
  • Aurora 64B/66B