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AR# 42805

LogiCORE IP Spartan-6 FPGA Triple-Rate SDI (Serial Digital Interface) - Release Notes and Known Issues

Description

This answer record contains the Release Notes and Known Issues list for the CORE Generator LogiCORE IP Triple Rate Serial Digital Interface (SDI) Core.

The following information is listed for each version of the core:

  • New Features
  • Bug Fixes
  • Known Issues

LogiCORE IP Triple Rate SDI:
http://www.xilinx.com/content/xilinx/en/products/intellectual-property/s6sdi.html

Solution

General LogiCORE IP Triple Rate SDI Issues

LogiCORE IP Spartan-6 FGPA Triple Rate SDI v1.0

  • Initial release in the ISE Design Suite 13.1

Supported Devices

  • Spartan-6 XC LXT
New Features
  • ISE 13.2 design tools support
  • First release of this core in the CORE Generator tool
Bug Fixes
  • N/A
Known Issues
  • (Xilinx Answer 44399) - Why do the rx_t_ signals say that the identity is not necessarily the same as the data?
  • (Xilinx Answer 47156) - Why can I not find the "hd sdi" protocol in the Spartan-6 GTP Transceiver Wizard?
  • (Xilinx Answer 52871) - How do I reset the Spartan 6 Triple SDI "sdi_drp_control" if the clock becomes unstable?
  • (Xilinx Answer 53539) - How many cycles does the crc_err_a and crc_err_b remain asserted?
  • (Xilinx Answer 53466) - How do I create constraints for the Spartan-6 Triple Rate SDI core?
  • (Xilinx Answer 55066) - Why does UG824 Figure 3.1 show TXUSRCLK connected to gtp_txusrclk2 and TXUSRCLK2 connected to gtp_txusrclk?

Linked Answer Records

Child Answer Records

Associated Answer Records

AR# 42805
Date Created 06/23/2011
Last Updated 11/10/2014
Status Active
Type General Article
Devices
  • Spartan-6 LXT
IP
  • Spartan-6 FPGA Triple-Rate SDI
  • Processing