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AR# 42808

MIG 7 Series v1.2 - Component switching limit error on PHY hard blocks due to incorrect timing model

Description

In ISE 13.2 software release, an error in the timing model for the PHASER and the PLL can causeincorrectcomponent switching limit errors on PHASER_OUT, PHASER_IN, OUT_FIFO, and IN_FIFOPHY hard blocks.

Solution

These errors can be safely ignored.

The component limit switching errors only occur on -1 and -2L speed grades for Kintex-7 and Virtex-7 devices.Following are some examples of the physical resources that could possibly show the error:

u_mig_7series_v1_2/u_memc_ui_top_std/mem_intfc0/phy_top0/u_mc_phy_wrapper/u_mc_phy/phy_4lanes_0.phy_4lanes/byte_lane_B.byte_lane_B/phaser_out/FREQREFCLK

u_mig_7series_v1_2/u_memc_ui_top_std/mem_intfc0/phy_top0/u_mc_phy_wrapper/u_mc_phy/phy_4lanes_0.phy_4lanes/byte_lane_A.byte_lane_A/phaser_in/FREQREFCLK

u_mig_7series_v1_2/u_memc_ui_top_std/mem_intfc0/phy_top0/u_mc_phy_wrapper/u_mc_phy/phy_4lanes_0.phy_4lanes/byte_lane_B.byte_lane_B/out_fifo/RDCLK

u_mig_7series_v1_2/u_memc_ui_top_std/mem_intfc0/phy_top0/u_mc_phy_wrapper/u_mc_phy/phy_4lanes_0.phy_4lanes/byte_lane_B.byte_lane_B/in_fifo/WRCLK

u_mig_7series_v1_2/u_memc_ui_top_axi/mem_intfc0/phy_top0/u_mc_phy_wrapper/u_mc_phy/phy_4lanes_1.phy_4lanes/byte_lane_B.byte_lane_B/phaser_in/MEMREFCLK

This issue is scheduled to be fixed in MIG 7 Series v1.3 inISE software release 13.3.

AR# 42808
Date Created 06/27/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
Devices
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG