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AR# 42810: LogiCORE IP DisplayPort v2.3 - Why does the reference design have timing violations?
LogiCORE IP DisplayPort v2.3 - Why does the reference design have timing violations?
Why does the reference design have timing violations?
This problem exists when an example design is used as is or in some cases when the video clock is sourced from external PLL (custom boards). It is due to a problem with the way that XST connects up the clock buffers.
You can work around this issue by adding a synthesis attribute to the video clock group to guide the tool to add BUFG as required. Here is the syntax: //synthesis attribute BUFFER_TYPE vid_clk BUFGP
Or, you can modify the design to include the use of some of the Spartan-6 FPGA clocking resources like the PLL or DCM to derive the video clock.
Please see (Xilinx Answer 33258) for a detailed list of LogiCORE IP DisplayPort Release Notes and Known Issues.