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AR# 42812

13.1 EDK - AXI_PLBv46_Bridge - Burst Length Mismatch on AXI and PLB


When performing a burst write transaction from AXI to PLB through the AXI_PLBv46_Bridge, I see mismatched data size on AXI interface and PLBinterface at the AXI_PLBv46_Bridge.

AXIInterface : 40 byte data (32-bit * 10 beat) burst
PLBInterface : 64 byte data (32-bit * 16 beat) burst

The data width of AXI_Interconnect is 256-bit, whileAXI_PLBv46_Bridge is 32-bit.

Is this a problem with the AXI_PLBv46_Bridge?


This is not a bug in the core. This can happen when you configure the AXI_PLBv46_Bridge in a different data width than the AXI_Interconnect data width.

There are two different work-arounds:

1. Match the data width of the bridge core and the interconnect.
2. Burst data size must be multiple of data width of the interconnect.

AR# 42812
Date 12/15/2012
Status Active
Type General Article
  • EDK - 13.1
  • AXI to PLBv46 Bridge
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