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AR# 4283

F1.4 Simulator: Simulating FPGA Express Netlist returns Warning 9218: unknown pin name


Keywords: Express, vhdl, verilog, simulate, unknown, pin, name, .gr, .ce, ldnode,
9218, Spartan

Urgency: Standard

General Description:

When loading a Spartan .xnf from FPGA Express in the
Foundation Logic Simulator, one of the following warnings occur

Warning 9218: LDNODE: <your register name>(FDCE).GR - Unknown pin name
Warning 9218: LDNODE: <your register name>(IFD).GR - Unknown pin name
Warning 9218: LDNODE: <your register name>(IFD).CE - Unknown pin name


The XNF file is valid. Running through the Xilinx Design
Manager Implementation tools creates valid bitstreams.

To functionally simulate the design, the design must first be
run through the Translate phase of the Implementation Tools,
then Checkpoint Simulation must be performed.

* Invoke the Design Manager by selecting the Implement button in
the Project Manager.
* Select Design -> New Version
* Select Design -> New Revision
* Invoke the Flow Engine by clicking on the Flow Engine icon in
Design Manager.
* Click the Step button in the Flow Engine to advance the flow through
just the Translate phase of the flow.
* Close the Flow Engine and return to the Project Manager
* Select Tools -> Checkpoint Simulation.
* Select the .NGD file of the Ver/Rev you just created.
* The Netlist will be translated and the design will be loaded in
the Simulator.
AR# 4283
Date Created 07/20/1998
Last Updated 04/04/2000
Status Archive
Type General Article