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AR# 42830

7 Series Integrated Block for PCI Express - sys_reset_n does not have a pin location constraint


Version Found: v1.1
Version Resolved and other Known Issues: See (Xilinx Answer 40469).

The generated UCF file does not locate the sys_reset_n pin to any particular pin. Starting in the ISE Design Suite13.2 software, if BitGen is run on a 7 Series design without a pin location, the following error occurs:

"ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD).This maycause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected.To prevent this error, it is highly suggested to specify all pin locations and I/O standards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you can apply the following bitgen switch: -g UnconstrainedPins:Allow."

Note: "Version Found" refers to the version the problem was first discovered. The problem may also exist in earlier versions, but no specific testing has been performed to verify earlier versions.


Users should choose a pin locationconvenient for their board design and locate the pin in the UCF.

It is important to note that it is possible to damage 7 Series devices if pins are not located correctly for their I/O standard. See (Xilinx Answer 41615) for more information.

Revision History
12/06/2011 - Added version resolved reference to AR 40469
07/06/2011 - Initial Release

AR# 42830
Date Created 06/24/2011
Last Updated 05/19/2012
Status Active
Type Known Issues
  • Virtex-7
  • Kintex-7