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AR# 42831

MIG 7 Series DDR3/QDRII+/RLDRAM II - Design Fails in Core Generation with Single-ended System Clock


Version Found: v1.2
Version Resolved and other Known Issues: See (Xilinx Answer 45195).

In certain configurations, MIG 7 Series does not show pins available to allocate the System Clock pins during the "System Signals Selection" page in the MIG GUI.

This prevents you from proceeding to generate the MIG core.


This is due to an efficiency issue with the MIG pin allocation algorithm that prevents available pins from being selected for System Clock.

To work around the problem, follow one of the provided solutions:

  • For Single-Ended System Clock designs:
    1. Select Differential System Clock.
    2. Choose available Pins in the "System Signals Selection" page for the System Clock and generate design.
    3. Comment out the unneeded System Clock pin in the generated UCF since single-ended is all that is needed.
    4. Change the top-level parameter INPUT_CLK_TYPE and set it to "SINGLE_ENDED".
  • For Single-Ended or Differential System Clock designs:
    1. Generate the design using the "New Design" option without selecting pins for the system clock pins.
    2. Regenerate the design using the "Fixed Pin Out" feature and import the UCF constraints from the previous design created.
    3. Select the system clock pins and regenerate the design.

Linked Answer Records

Associated Answer Records

AR# 42831
Date Created 06/24/2011
Last Updated 08/28/2014
Status Active
Type Known Issues
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
  • MIG