The JEDEC specifications state that a maximum of eight refreshes can be postponed up to 9*tREFI periods, and after that refreshes should be pulled in to meet the tREFI time. The MIG 7 Series v1.2-v1.4 DDR3 design is violating this specification when SIM_BYPASS_INIT_CAL="SIM_INIT_CAL_FULL".
There is currently no workaround, so these violations can be ignored for now.
This issue is to be fixed in MIG v1.5 to be released in ISE 14.1 software.