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AR# 42833 MIG 7 Series v1.2-v1.5 DDR3 - Parity error for RDIMM designs during memory initialization and calibration process

Description

A parity error is generated for RDIMM designs during the memory initialization and calibration process for DDR3 SDRAM designs.

Solution

This is due to an issue in the RTL code, and this error can be safely ignored. Parity error reports properly once the calibration is completed (that is, after init_calib_complete is asserted).

This issue is scheduled to be fixed in MIG 7 Series 1.6 in ISE software release 14.2.

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AR# 42833
Date Created 06/27/2011
Last Updated 04/23/2012
Status Active
Type
Devices
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG
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