Note: The problem below affects Verilog only and does not affect the VHDL top-level module.
The Verilog version of the v_triple_sdi_1_0 core does not drive the GTX TXRESET_IN pin correctly when the GTX TX buffer under or overflows.
This is caused by an error in connecting the GTX TXBUFSTATUS bit to drive the GTX TXRESET_IN port in the triple_sdi_rxtx_top.v file.
When the v_triple_sdi_v1_0 core is generated, the file is located at: <ise_project_dir>\ipcore_dir\<core_name>\hdl\triple_sdi_rxtx_top.v
To work around this problem, you must modify the signal connected to the txbufstatus1 port of the v6gtx_sdi_control module from gtx_txbufstatus to gtx_txbufstatus1 as shown below.
(This is located on line 508 of the triple_sdi_rxtx_top.v file)
Please see (Xilinx Answer 40473) for a detailed list of the LogiCORE IP Triple Rate SDI Release Notes and Known Issues.