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AR# 42871

13.2 ISE Simulator: Cannot handle forcing values to arrays for some types correctly, for example std_logic_vector and record

Description

ISE Simulator cannot handle forcing values to arrays of some types correctly, such as std_logic_vector and record.

Two examples below illustrate this:

Example 1:
 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ybd is

end ybd;

architecture Behavioral of ybd is

      type t_ybd is array (7 downto 0) of std_logic_vector(3 downto 0);

      signal ybd: t_ybd;

begin

end Behavioral;

Example 2:
 

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity ybd is

end ybd;

architecture Behavioral of ybd is

    type r_ybd is

        record

      ybd:std_logic;

        end record;

      type t_ybd is array (7 downto 0) of r_ybd;

      signal ybd: t_ybd;

begin

end Behavioral;

 


Solution

You may force values to these arrays but only forcing ybd[7] will be effective. 

This issue is still seen in the 13.2 release and a CR has ben filed against the problem.

The suggested work around is to avoid using these array types and use multiple records instead.

AR# 42871
Date Created 06/28/2011
Last Updated 10/01/2014
Status Active
Type General Article
Tools
  • ISE Design Suite - 13.1
  • ISE Design Suite - 13.2