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AR# 42883

LogiCORE SPI-4.2 (POS-PHY L4) - Timing Simulation Setup and Hold Errors Seen when Using Static Alignment


When the sink core is configured for static alignment during timing simulation, it might be possible to encounter setup errors on the data input. An example error message is as follows:

 " ** Error pl4_demo_testbench.pl4_wrapper0.\core_pl4_snk_top0/U0/io0/chan17/U1.xsetuphold_chk $setup(CLK 437466 ps, D 437411 ps, 866 ps )"


If timing checks are turned off, the symptom that you see is that the sink core never goes in frame and SnkBusErr (SnkBusErrStat[3] and [5]) are asserted. The phase shift setting provided with the SPI-4.2 core in the constraints file is only a place-holder and might not be appropriate for all designs. See the section "Designing with the Core" in the LogiCORE SPI-4.2 User Guide for more information.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
42572 SPI-4.2 v10.5 - Release Notes and Known Issues for ISE Design Suite 13.2 N/A N/A
AR# 42883
Date 05/26/2014
Status Archive
Type General Article
  • SPI-4 Phase 2 Interface Solutions