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AR# 42899

Partial Reconfiguartion - Can I insert ChipScope cores within Reconfigurable Modules?

Description

Can I insert ChipScope cores within Reconfigurable Modules?

Solution

The ICON core must remain in the static part of the design. It uses a global clock buffer which must remain part of the top level clocking. It also uses a BSCAN element, which is recommended (required in 7 series) to remain in static logic.

ILA or VIO cores may be placed inside Reconfigurable Modules, but a special consideration must be taken to connect these to the ICON. The CONTROL bus that connects these elements is defined as bidirectional, to simplify HDL instantiation. In truth, this bus is actually a collection of 35 signals going from ICON to ILA, and one signal going the opposite direction. Bidirectional signals are not permitted on Reconfigurable Partition interfaces due to proxy logic insertion, so a wrapper for each ChipScope must be created to convert these inout ports to inputs and outputs.

When inserting ILA cores within Reconfigurable Partitions, note that extra slice and BRAM logic will be required to implement the core alongside your logic. PlanAhead tool resource reports can help you ensure you have selected an appropriate region.

Here are examples of wrappers for ICON, ILA and VIO cores. Only the CONTROL port definitions have been modified from the standard core templates. Use these as you would standard ChipScope core instantiation. Pass the CONTROL_TO_ICON and CONTROL_TO_ILA ports through the Reconfigurable Partition interface to connect the ICON above and the ILA (or VIO) below. These wrappers must be adjusted for different trigger or data bus sizes on the ILA, data inputs or outputs to the VIO, or the number of CONTROL buses required on the ICON.


ICON wrapper:

module icon_wrapper (CONTROL_TO_ICON, CONTROL_TO_ILA);
input CONTROL_TO_ICON;
output [34:0] CONTROL_TO_ILA;

wire [35:0] CONTROL;

assign CONTROL_TO_ILA[2:0] = CONTROL[2:0];
assign CONTROL_TO_ILA[34:3] = CONTROL[35:4];
assign CONTROL[3] = CONTROL_TO_ICON;

//instantiation of ICON core

icon_1 icon_inst (.CONTROL0(CONTROL));
endmodule

//module declaration

module icon_1 (CONTROL0);
inout [35:0] CONTROL0;
endmodule

ILA wrapper:

module ila_wrapper(CONTROL_TO_ICON, CONTROL_TO_ILA, CLK, DATA, TRIG0);
output CONTROL_TO_ICON;
input [34:0] CONTROL_TO_ILA;
input CLK;
input [31:0] DATA; //data bus size will change per core
input [7:0] TRIG0; //trigger bus size will change per core

wire [35:0] CONTROL;

assign CONTROL[2:0] = CONTROL_TO_ILA[2:0];
assign CONTROL[35:4] = CONTROL_TO_ILA[34:3];
assign CONTROL_TO_ICON = CONTROL[3];

//instantiation of ILA core

ila_1 ila_inst (
.CONTROL(CONTROL),
.CLK(CLK),
.DATA(DATA),
.TRIG0(TRIG0));
endmodule

//module declaration

module ila_1 (CONTROL, CLK, DATA, TRIG0);
inout [35:0] CONTROL;
input CLK;
input [7:0] DATA;
input [3:0] TRIG0;
endmodule

VIO wrapper:

module vio (CONTROL_TO_ICON, CONTROL_TO_ILA, CLK, ASYNC_IN, SYNC_IN, ASYNC_OUT, SYNC_OUT);
output CONTROL_TO_ICON;
input [34:0] CONTROL_TO_ILA;
input CLK;
input [7:0] ASYNC_IN; //data input size will change per core
input [7:0] SYNC_IN; //data input size will change per core
output [7:0] ASYNC_OUT; //data output size will change per core
output [7:0] SYNC_OUT; //data output size will change per core

wire [35:0] CONTROL;

assign CONTROL[2:0] = CONTROL_TO_ILA[2:0];
assign CONTROL[35:4] = CONTROL_TO_ILA[34:3];
assign CONTROL_TO_ICON = CONTROL[3];

//instantiation of VIO core

vio_1 vio_inst (
.CONTROL(CONTROL),
.CLK(CLK),
.ASYNC_IN(ASYNC_IN),
.ASYNC_OUT(ASYNC_OUT),
.SYNC_IN(SYNC_IN),
.SYNC_OUT(SYNC_OUT));
endmodule

//module declaration

module vio_1 (CONTROL, CLK, ASYNC_IN, ASYNC_OUT, SYNC_IN, SYNC_OUT);
inout [35:0] CONTROL,
input CLK,
input [7:0] ASYNC_IN,
output [7:0] ASYNC_OUT,
input [7:0] SYNC_IN,
output [7:0] SYNC_OUT);
endmodule
AR# 42899
Date Created 06/30/2011
Last Updated 12/08/2011
Status Active
Type General Article
Tools
  • PlanAhead - 13.0
  • PlanAhead - 13.1
  • PlanAhead - 13.2