We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 42900

7 Series Integrated Block Wrapper for PCI Express - How do I implement the example design in PlanAhead?


How do Iimplement the example design in PlanAhead?


Follow the steps below to implement a 7 Series Integrated Block Wrapper for the PCI Express core example design in PlanAhead:

1. Create an empty project.

2. Set the target device.

3. Click "IP Catalog."

4. Select the language options for the core as shown below by clicking "IP Catalog Settings."

5. Customize the core by clicking "Customize IP."

After the core has been customized, the XCO, VHO, and TCL files are added to the project, in the "Sources" window as shown below.

6. Generate the core by selecting the "Generate IP" option by right clicking on the .xco file:

7. Add the generated source files into the project.

8. Add the UCF file.

9. Select the top-level module as shown below.

10. Click on the "Implementation Settings" to change the NGDBuild, MAP, and PAR options.

11. Implement the design by clicking the "Implement" button.

It gives you an option to generate the bit file as shown below. Select "Generate Bitstream" and click OK to generate the bit file.

Revision History 06/29/2011
- Initial Release
AR# 42900
Date Created 07/01/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • ISE Design Suite - 13.1
  • Endpoint Block Wrapper for PCI Express