Simulation does not work correctly when simulating in ISIM with either cascaded AXI interconnects or an AXI master that have an ID width greater than 1. However, structural simulations or hardware tests do run correctly. Simulations in ModelSim also work correctly.
How do I resolve this issue?
This problem occurs becauseISIM is not correctly passing parameters which configure ID vector widths to the AXI interconnect slave ports (for master peripherals), causingtransactions to be routed incorrectly during ISIM simulation.Cascaded interconnects are affected since the upstream interconnect typically has a wider AXI ID width.
This issue is scheduled to be fixed in the ISE 13.3 software release.