A simulation netlist is needed for simulation.
The edif source must be converted to a Xilinx design file in the form of an NGC, NGD or NCD, so that NetGen can take the file as input and write out a single netlist for the entire design.
To run Post-Synthesis (Pre-NGDBuild) Gate-Level Simulation, use the ngcbuild command to convert all of the design netlists to a single NGC file.
The following command reads the top-level EDIF netlist and converts it to an NGC file:
ngcbuild [options] top_level_netlist_file output_ngc_file
Then, enter the NGC file as input on the NetGen command line to generate a Verilog or VHDL Post-Synthesis Simulation netlist.
To run Post-NGDBuild, Post-Map or Post-Place & Route Simulation, you can run NGDBuild, MAP or PAR using the EDIF source.
After that, enter the NGD or NCD file produced in the previous step as input on the NetGen command line to generate a Verilog or VHDL Post-NGDBuild, Post-MAP or Post- Place & Route Simulation netlist.
Alternatively, you can create an ISE project with top-level source type set to EDIF.
This allows you to perform Post-Translate, Post-MAP or post-Route simulation directly from within Project Navigator.
For more usage information on the NetGen command, please refer to (UG628) Command Line Tools User Guide.