Design Advisories Alerted on April 3, 2013
04/03/2013 - (Xilinx Answer 55009) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode
03/26/2013 - (Xilinx Answer 51625) Design Advisory for Virtex-7 FPGA GTH General ES Transceiver: Updated RX_DFE_KL_CFG setting
04/03/2013 - (Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT, 690XT - Bitstream compatibility requirements between GES and Production devices: Updated for 7V690T production devices

Design Advisory Alerted on March 19, 2013
03/07/2013 - (Xilinx Answer 51625) Updated Design Advisory for Virtex-7 FPGA GTH General ES Transceiver: Updated LPM port settings to be in adapt mode, Changed QPLL_CFG setttings from "line rate" to QPLL frequency

Design Advisory Alerted on February 25, 2013
02/21/2013 - (Xilinx Answer 53779) Updated Design Advisory for Virtex-7 FPGA GTH Production Transceiver RX Reset Sequence Requirement to reflect the correct GTH mode combination where the new reset is required

Design Advisory Alerted on February 18, 2013
02/15/2013 - (Xilinx Answer 51625) Updated Design Advisory for Virtex-7 FPGA GTH General ES Transceiver: Added RXCDR_CFG setting for PCIe Gen3, updated DFE port settings to be in adapt mode

Design Advisory Alerted on February 11, 2013
02/04/2013 - (Xilinx Answer 47128) Updated Design Advisory for Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon; added PCS_RSVD_ATTR[8] and note

Design Advisory Alerted on February 4, 2013
01/31/2013 - (Xilinx Answer 53779) Design Advisory for Virtex-7 FPGA GTH Transceiver: RX Reset Sequence Requirement for Production Silicon

Design Advisory Alerted on January 21, 2013
01/17/2013 - (Xilinx Answer 53740) Updated Design Advisory for 7 Series Xilinx PCI Express Cores - No Clock Output on TXOUTCLK at Cold Temperature.

Design Advisories Alerted on January 14, 2013
01/09/2013 - (Xilinx Answer 51625) Updated Design Advisory for Virtex-7 FPGA GTH General ES Transceiver: updated BIAS_CFG, QPLL_CFG settings and added QPLL_CLKOUT_CFG to the table.

Design Advisories Alerted on December 18, 2012
12/13/2012 - (Xilinx Answer 51625) Updated Design Advisory for Virtex-7 FPGA GTH General ES Transceiver: added the RXCDR_CFG setting for SATA SSC and a note on RXELECIDLEMODE/RXBUF_RESET_ON_EIDLE when not using OOB.
12/13/2012 - (Xilinx Answer 45360) Updated Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX General ES Transceiver: added the RXCDR_CFG setting for SATA SSC and a note on RXELECIDLEMODE/RXBUF_RESET_ON_EIDLE when not using OOB.

Design Advisory Alerted on November 13, 2012
11/09/2012 - (Xilinx Answer 47443) Updated Table 1 in the Design Advisory for the Virtex-7 GTH Transceiver Power-up/Power-down to include all devices and packages

Design Advisories Alerted on November 5, 2012
10/31/2012 - (Xilinx Answer 50617) Updated Design Advisory for Kintex-7 and Virtex-7 FPGA Production GTX Transceivers with references to specific devices; updated the bitstream compatibility section
10/25/2012 - (Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode
10/25/2012 - (Xilinx Answer 51625) Updated Design Advisory for Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues and Work-arounds for General Engineering Sample (ES) Silicon; added RXCDR_CFG values for 8B/10B

Design Advisories Alerted on October 18, 2012
10/17/2012 - (Xilinx Answer 51625) Design Advisory for Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues and Work-arounds for General Engineering Sample (ES) Silicon
10/17/2012 - (Xilinx Answer 51884) Design Advisory for Kintex-7 and Virtex-7 FPGA GTX Production Silicon CDR Attribute Updates
10/17/2012 - (Xilinx Answer 47128) Updated Design Advisory for Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon; added the ACJTAG use mode

Design Advisory Alerted on September 10, 2012
09/10/2012 - (Xilinx Answer 51580) Design Advisory for 14.1/14.2 Timing Analysis 7 Series FPGA - Clock Arrival Times are Incorrect for Block Ram (BRAM) or FIFO Components for PERIOD constraint analysis

Answer Records Upgraded to Design Advisory
09/10/2012 - (Xilinx Answer 45781) Design Advisory for 7 Series XADC - Using the XADCEnhancedLinearity BitGen option
09/10/2012 - (Xilinx Answer 44971) Design Advisory for 7 Series XADC - Accuracy of On Chip Reference

Design Advisories Alerted on August 20, 2012
08/20/2012 - (Xilinx Answer 51296) Design Advisory - 7 Series Package Flight Time Changes in ISE 14.2 and Vivado 2012.2 Design Suite releases
08/17/2012 - (Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T, and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices
08/17/2012 - (Xilinx Answer 47443) Updated Design Advisory for the Virtex-7 GTH Transceiver Power-up/Power-down with updated V_MGTAVTT additional current draw value

Design Advisory Alerted on August 13, 2012
08/10/2012 - (Xilinx Answer 47128) Updated Design Advisory for Virtex-7 GTH Initial ES Transceiver with example GTHE2_COMMON instantiations on the GTHE2_COMMON/BIAS_CFG section and added some references to ISE 14.2/Vivado 2012.2 in general.

Design Advisory Alerted on July 30, 2012
07/27/2012 - (Xilinx Answer 47128) Updated Design Advisory for Virtex-7 GTH Initial ES Transceiver that there is no issue with GTH Resistor Calibration and no work-around is required.

Design Advisories Alerted on July 25, 2012
07/19/2012 - (Xilinx Answer 47443) Updated Design Advisory for the Virtex-7 GTH Transceiver Power-up/Power-down with information about duration of current draw, simultaneous power-up and more FAQs.
07/19/2012 - (Xilinx Answer 47817) Updated Design Advisory for the Kintex-7/Virtex-7 GTX Transceiver Power-up/Power-down with additional current draw when following the recommended sequence, information about duration of current draw, simultaneous power-up and more FAQs.
07/19/2012 - (Xilinx Answer 45360) Updated Design Advisory for the Kintex-7and Virtex-7 FPGA GTX General ES Transceiver with RX_DFE_XYD_CFG value.
07/19/2012 - (Xilinx Answer 50617) Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceivers.

Design Advisory Alerted on July 16, 2012
07/12/2012 - (Xilinx Answer 47128) Updated Design Advisory for Virtex-7 GTH Initial ES Transceiver with updated QPLL_CFG and QPLL_LOCK_CFG values and GTH Transceiver Link Margin Reduction section.

Design Advisories Alerted on July 2, 2012
06/28/2012 - (Xilinx Answer 47817) Design Advisory for the Kintex-7/Virtex-7 GTX Transceiver Power-up.
06/28/2012 - (Xilinx Answer 47128) Updated Design Advisory for Virtex-7 GTH Initial ES Transceiver to include latest PMA_RSV2, RX_BIAS_CFG, RXDFEXYDEN values in the attributes and ports section.
06/28/2012 - (Xilinx Answer 45360) Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon.

Design Advisory Alerted on June 11, 2012
06/08/2012 - (Xilinx Answer 47443) Updated the Design Advisory for 7 series FPGAs GTH Transceiver Power up.

Design Advisory Alerted on May 28, 2012
05/24/2012 - (Xilinx Answer 47128) Updated Design Advisory to include GTHE2_COMMON and termination use modes, the Initial ES errata items section, and updated the resistor calibration section.

Design Advisory Alerted on May 15, 2012
05/14/2012 - (Xilinx Answer 47128) Updated Design Advisory title to "Virtex-7 FPGA GTH Transceiver - Attribute Updates, Issues, and Work-arounds for Initial Engineering Sample (ES) Silicon" and included the Resistor Calibration section and updated BIAS_CFG setting

Design Advisories Alerted on May 8, 2012
05/03/2012 - (Xilinx Answer 47128) Design Advisory for Virtex-7 FPGA GTH Transceiver - Attribute Updates and Use Modes for Initial Engineering Sample (ES) Silicon
05/03/2012 - (Xilinx Answer 47443) Design Advisory for 7 series FPGAs GTH Transceiver - Static Power Errata

Design Advisory Alerted on April 30, 2012
4/30/2012 - (Xilinx Answer 47342) Design Advisory for Virtex-7 GTH Serial Transceiver Package Diagram corrections

Design Advisory Alerted on January 16, 2012
01/10/2012 - (Xilinx Answer 45633) Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified

Design Advisory Alerted on November 21, 2011
11/21/2011 - (Xilinx Answer 44174) Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup

Design Advisory Alerted on July 6, 2011
07/06/2011 - (Xilinx Answer 42615) Design Advisory for 7 Series FPGA Transceivers - GTX Port Name Changes in ISE 13.2 Design Suite

Revision History

04/03/2013 - Added 55009. Updated 51625 and 50906
03/07/2013 - Updated 51625
02/21/2013 - Updated 53779
02/15/2013 - Updated 51625
02/04/2013 - Updated 47128
01/31/2013 - Added 53779
01/17/2013 - Added 53740
01/16/2013 - Added 53788
01/09/2013 - Updated 51625
12/13/2012 - Updated 51625 and 45360
11/09/2012 - Updated 47443
10/31/2012 - Added 52193 and updated 51625, 50617
10/18/2012 - Added 51625, 51884, and updated 47128
09/10/2012 - Added 51508. Upgraded 45781 and 44971 to Design Advisories.
08/20/2012 - Added 50906 and 51296. Updated 47443
08/13/2012 - Updated 47128
07/30/2012 - Updated 47128
07/19/2012 - Updated 47443, 47817, 45360 and added 50617
07/12/2012 - Updated 47128
06/28/2012 - Added 47817
06/28/2012 - Updated 47128
06/28/2012 - Added 45360
06/11/2012 - Updated 47443
05/28/2012 - Updated 47128
05/15/2012 - Updated 47128
05/08/2012 - Added 47128 and 47443
04/30/2012 - Added 47342
01/10/2012 - Added 45633
12/12/2011 - Updated title for 44174
11/21/2011 - Added 44174
07/06/2011 - Initial release