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AR# 42946

Design Advisory Master Answer Record for Kintex-7 FPGA

Description

Design Advisory Answer Records are created for issues that are important to designs currently in progress and are selected to be included in the Xilinx Alert Notification System.

This Design Advisory covers the Kintex-7 devices and related issues that impact Kintex-7 FPGA designs.

Solution

Design Advisories Alerted on April 17th, 2017

04/17/2017(Xilinx Answer 69034) Design Advisory for 7 Series, UltraScale and UltraScale+, all versions of Vivado prior to 2016.3 failed to include Flight time delays for differential IO Standards.

Design Advisories Alerted on March 28, 2016

03/28/2016(Xilinx Answer 66173)Design Advisory for Vivado 2015.4 - Vivado Timing WNS Alert - Missing Timing Arc on BUFR to BUFG clock path causes hold violations on board

Design Advisories Alerted on November 10, 2014

11/10/2014(Xilinx Answer 62631)Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 series and UltraScale FPGAs

Design Advisories Alerted on September 22, 2014

09/22/2014(Xilinx Answer 61875)Design Advisory for QPLL based 7 Series FPGA GTX/GTH designs: QPLLPD should not be enabled for min time of 500ns after configuration is complete.

Design Advisories Alerted on June 16, 2014

06/16/2014(Xilinx Answer 60845)Design Advisory for MIG 7 Series RLDRAM3 - SIM_BYPASS_INIT_CAL incorrectly set to "FAST" for synthesis and implementation
06/16/2014 (Xilinx Answer 59294)Design Advisory GT wizard - CPLL causes power spike on power up for 7 series Transceivers

Design Advisories Alerted on May 26, 2014

05/26/2014(Xilinx Answer 60356)Design Advisory for 7 Series FPGAs Transceivers Wizard v3.2 or earlier - Required XDC constraint Updates
05/26/2014(Xilinx Answer 45360)Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Updated the RXCDR_CFG setting for SATA Gen 2/Gen 3 and PMA_RSV for 6.6 Gbps

Design Advisory Alerted on January 20, 2014

01/20/2014(Xilinx Answer 59035)Design Advisory for 7 Series FPGA GTX/GTH Transceivers - QPLL not supported for PCIe Gen1/Gen2

Design Advisories Alerted on November 25, 2013

11/25/2013(Xilinx Answer 58244)Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode
11/25/2013(Xilinx Answer 45360)Updated Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX General ES Transceiver; added reference to the user guide UG476 for RX_DFE_KL_CFG2 setting

Design Advisory Alerted on October 23, 2013

10/23/2013(Xilinx Answer 51554)Design Advisory for Aurora 64B66B v8.1 or earlier - Core initialization is inconsistent on consecutive RESET and PMA_INIT inputs

Design Advisory Alerted on September 16, 2013

09/16/2013(Xilinx Answer 57193)Design Advisory for the Artix-7, Kintex-7, Virtex-7, Zynq-7000 Packaging - The 7 Series Thermal Resistance Values (Theta-JA, Theta-JB, and Theta-JC) are being updated with more accurate values, many of which are substantially changed

Design Advisory Alerted on August 26, 2013

08/19/2013(Xilinx Answer 57045)Design Advisory for Artix-7/Kintex-7 - When CFGBVS is set to VCCO of Bank 0, then Banks 14 and 15 are limited to 3.3V or 2.5V for Configuration

Design Advisory Alerted on August 5, 2013

08/05/2013(Xilinx Answer 55009) Updated Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode with links to Answer Records for IPs

Design Advisory Alerted on May 20, 2013

05/16/2013(Xilinx Answer 55009) Updated Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode with links to Answer Records for IPs

Design Advisories Alerted on May 13, 2013

05/13/2013(Xilinx Answer 55366) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - Transceiver Wizard Sets Suboptimal RX Termination Use Modes
05/13/2013(Xilinx Answer 55791) Design Advisory for 7 Series FPGAs Transceivers Wizard - Required Updates to Wizard v2.5

Design Advisories Alerted on April 3, 2013

04/03/2013(Xilinx Answer 55009) Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers - TX Sync Controller Change for Phase Alignment in Buffer Bypass Mode
04/03/2013(Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT, 690XT - Bitstream compatibility requirements between GES and Production devices: Updated for 7V690T production devices

Design Advisory Alerted on January 21, 2013

1/17/2013(Xilinx Answer 53740) Updated Design Advisory for 7-Series Xilinx PCI Express Cores - No Clock Output on TXOUTCLK at Cold Temperature.

Design Advisory Alerted on December 18, 2012

12/13/2012(Xilinx Answer 45360) Updated Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX General ES Transceiver: added the RXCDR_CFG setting for SATA SSC and a note on RXELECIDLEMODE/RXBUF_RESET_ON_EIDLE when not using OOB.

Design Advisories Alerted on November 5, 2012

10/31/2012(Xilinx Answer 50617) Updated Design Advisory for Kintex-7 and Virtex-7 FPGA Production GTX Transceivers with references to specific devices; updated the bitstream compatibility section
10/25/2012(Xilinx Answer 50906) Updated Design Advisory for Production Kintex-7 325T, 410T and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices; updated for 14.3/2012.3 release

Design Advisories Alerted on October 29, 2012

10/25/2012(Xilinx Answer 52193) Design Advisory for 7 Series BPI Multiboot - When fallback occurs flash access is always in BPI asynchronous Mode

Design Advisories Alerted on October 22, 2012

10/22/2012(Xilinx Answer 45360) Updated the RXCDR_CFG values in the Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX General ES Transceiver
10/22/2012(Xilinx Answer 50617) Updated the bitstream compatibility section in the Design Advisory for the Kintex-7 and Virtex-7 FPGA Production GTX Transceiver

Design Advisory Alerted on October 15, 2012

10/15/2012(Xilinx Answer 51884) Design Advisory for Kintex-7 and Virtex-7 GTX Production Silicon CDR Attribute Updates

Design Advisory Alerted on September 10, 2012

09/10/2012(Xilinx Answer 51580) Design Advisory for 14.1/14.2 Timing Analysis 7 Series - Clock Arrival Times are Incorrect for block Ram (BRAM) or FIFO Components for PERIOD constraint analysis

Answer Records Upgraded to Design Advisories

09/10/2012(Xilinx Answer 45781) Design Advisory for 7 Series XADC - Using the XADCEnhancedLinearity BitGen option
09/10/2012(Xilinx Answer 44971) Design Advisory for 7 Series XADC - Accuracy of On Chip Reference

Design Advisory Alerted on August 20, 2012

08/17/2012(Xilinx Answer 50906) Design Advisory for Production Kintex-7 325T, 410T and Virtex-7 485XT - Bitstream compatibility requirements between GES and Production devices
08/20/2012(Xilinx Answer 51296) Design Advisory - 7 Series Package Flight Time changes in ISE 14.2 and Vivado 2012.2 release

Design Advisories Alerted on July 25, 2012

07/19/2012(Xilinx Answer 47817) Updated Design Advisory for the Kintex-7/Virtex-7 GTX Transceiver Power-up/Power-down with additional current draw when following the recommended sequence, with information about duration of current draw, simultaneous power-up and more FAQs.
07/19/2012(Xilinx Answer 45360) Updated Design Advisory for the Kintex-7and Virtex-7 FPGA GTX General ES Transceiver with RX_DFE_XYD_CFG value.
07/19/2012(Xilinx Answer 50617) Design Advisory for the Kintex-7and Virtex-7 FPGA Production GTX Transceivers.

Design Advisories Alerted on July 2, 2012

06/28/2012(Xilinx Answer 47817) Design Advisory for the Kintex-7/Virtex-7 GTX Transceiver Power-up.
06/28/2012(Xilinx Answer 45360) Updated Design Advisory for the Kintex-7and Virtex-7 FPGA GTX Transceiver General Engineering Sample (ES) Silicon - Updated GTX software use mode changes (Xilinx Answer 43339) with the latest GTXE2_COMMON use model change information.

Design Advisory Alerted on May 8, 2012

05/07/2012(Xilinx Answer 47248) Design Advisory for the Kintex-7 FPGA - XC7K325T CES9937 Initial Engineering Sample (IES) Supported in ISE 13.4 only

Design Advisory Alerted on March 26, 2012

03/22/2012(Xilinx Answer 45360) Design Advisory for the Kintex-7and Virtex-7 FPGA GTX Transceiver General Engineering Sample (ES) Silicon - Updated RXCDR_CFG setting for half-rate mode.

Design Advisory Alerted on February 27, 2012

02/23/2012(Xilinx Answer 45360) Updated Design Advisory for the Kintex-7 and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon to include new RXCDR_CFG settings and a link to GTX software known issues/use mode changes.

Design Advisory Alerted on January 30, 2012

01/24/2012(Xilinx Answer 45360) Design Advisory for the Kintex-7and Virtex-7 FPGA GTX Transceiver - Attribute Updates, Issues, and Work-arounds for General Engineering Sample (ES) Silicon

Design Advisory Alerted on January 16, 2012

01/10/2012(Xilinx Answer 45633) Design Advisory for 7 Series MIG DDR3/DDR2 - Updated pin placement rules for CKE and ODT; existing UCFs must be verified

Design Advisory Alerted on November 21, 2011

11/21/2011(Xilinx Answer 44174) Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup

Design Advisory Alerted on October 17, 2011

10/17/2011(Xilinx Answer 44421) Design Advisory for 13.2 iMPACT - Incorrect indirect programming core file is loaded to Kintex-7 leading to potential device damage

Design Advisory Alerted on July 6, 2011

07/06/2011(Xilinx Answer 42615) Design Advisory for 7 Series FPGA Transceivers - GTX Port Name Changes in ISE 13.2 design tools

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
46370 Xilinx 7 Series FPGA Solution Center N/A N/A
47787 Design Advisory Master Answer Record for Kintex-7 FPGA KC705 Evaluation Kit N/A N/A

Child Answer Records

Answer Number Answer Title Version Found Version Resolved
44421 Design Advisory for 13.2 iMPACT - Incorrect indirect programming core file is loaded to Kintex-7 leading to potential device damage N/A N/A
44174 Design Advisory for techniques on properly synchronizing flip-flops and SRLs after startup N/A N/A
50906 Design Advisory for Production Kintex-7 325T, 410T, 420T and Virtex-7 485XT, 690XT, 1140XT - Bitstream compatibility requirements between GES and Production devices N/A N/A
51580 Design Advisory for 14.1/14.2 Timing Analysis 7 Series - Clock Arrival Times are Incorrect for Block RAM (BRAM) or FIFO Components for PERIOD constraint analysis N/A N/A
45781 Design Advisory for 7 Series XADC - Using the XADCEnhancedLinearity BitGen option N/A N/A
44971 Design Advisory for 7 Series XADC - Accuracy of On Chip Reference N/A N/A
52193 Design Advisory for 7 Series BPI Multiboot - When fallback occurs, flash access is always in BPI Asynchronous Mode N/A N/A
53740 Design Advisory for 7 Series Xilinx PCI Express Cores - No Clock Output on TXOUTCLK at Cold Temperature N/A N/A
55791 Design Advisory for 7 Series FPGAs Transceivers Wizard - Required Updates to Wizard v2.5 N/A N/A
55366 Design Advisory for 7 Series FPGA GTX/GTH/GTP Transceivers: Transceiver Wizard Sets Suboptimal RX Termination Use Modes N/A N/A
57193 Design Advisory for Artix-7, Kintex-7, Virtex-7, Zynq-7000 Packaging - The 7 Series Thermal Resistance Values (Theta-JA, Theta-JB, and Theta-JC) are being updated with more accurate values, many of which are substantially changed N/A N/A
51554 Design Advisory for Aurora 64B66B v8.1 or earlier - Core initialization is inconsistent on consecutive RESET and PMA_INIT inputs N/A N/A
58244 Design Advisory for 7 Series FPGA GTX Transceiver - RXDFEXYDEN Port Update in DFE Mode N/A N/A
59035 Design Advisory for 7 Series FPGA GTX/GTH Transceivers - QPLL not supported for PCIe Gen1/Gen2 N/A N/A
62631 Design Advisory for Vivado 2014.3 - Program eFUSE Registers operation failure for 7 series and UltraScale FPGAs N/A N/A

Associated Answer Records

AR# 42946
Date 06/27/2017
Status Active
Type Design Advisory
Devices
  • Kintex-7