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AR# 43010

Virtex-6 ISERDES/OSERDES - Using separate clock resources for ISERDES (OCLK) and OSERDES (CLK)


If I use a bi-directional interface targeting Virtex-6 FPGAwith the ISERDES and OSERDES in a single IOB, can the OCLK of the ISERDES (in Memory Interface mode) and the CLK of the OSERDES use two different clock nets?


No. The CLK of the OSERDES and the OCLK of the ISERDES must share the same clock.There is not enough routing resources available inside the IOB, and using separate clock nets for each clock input does not work in hardware.
AR# 43010
Date 12/15/2012
Status Active
Type General Article
  • Virtex-6 CXT
  • Virtex-6 HXT
  • Virtex-6 LX
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