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AR# 43017

FIFO Generator v8.2 - Behavioral Simulation model does not read data out properly with Built-In FIFO and embedded registers


Known Issue: v8.2, v8.1

When the FIFO Generator v8.2 core is configured to use a Built-In FIFO and using the embedded registers, the latency of the data out is not correct in the behavioral simulation model. 


This is a known issue with the core.

The core should have a read latency of two cycles, however, when the core is configured in this manner, there is a read latency of only one clock cycle. 

To work around this issue, use the structural simulation model instead of the behavioral model.

Release Notes:
07/06/2011 - Initial Release
AR# 43017
Date Created 07/06/2011
Last Updated 09/10/2014
Status Active
Type General Article
  • FIFO Generator