UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 43034

ISE SysGen - Sample Frequencies are incorrect when multiple subsystem designs with shared memories are used.

Description

Known issue: ISE System Generator

System Generator has a known issue when displaying sample frequencies. 

The known issue only occurs when a shared memory is shared between two subsystems with different FPGA Clock Periods.

Solution

The frequencies are displayed incorrectly, however, they are correct when generating files or simulating. 

For this reason, it is safe to ignore the frequencies that are displayed in the model.

This does not affect Vivado as Shared Memories are not available in Vivado Sysgen.

Revision History:
07/07/2011 - Initial Release
AR# 43034
Date Created 07/07/2011
Last Updated 09/02/2014
Status Active
Type Known Issues
Tools
  • System Generator for DSP - 14
  • System Generator for DSP - 13