We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 43058

LogiCORE IP Ethernet 1000BASE-X PCS/PMA or SGMII v11.1 - Why does the Example Design fail in bitgen when targeting Virtex-7 or Kintex-7 devices


When I generate a Virtex-7 or Kintex-7 device bitstream for the 10-Gigabit Ethernet MAC example design, the following error message occurs:

"ERROR:Bitgen:342-This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD).This maycause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected.To prevent this error, it is highly suggested to specify all pin locations and I/Ostandards to avoid potential contention or conflicts and allow proper bitstream creation. To demote this error to a warning and allow bitstream creation with unspecified I/O location or standards, you can apply the following bitgen switch: -g UnconstrainedPins:Allow."


Starting in the 13.2 software,this error message occurs if any of the pins do not have a location constraint or IOSTANDARD assigned.

For more information about the error message and how to downgrade this to a warning message if needed, please refer to(Xilinx Answer 41615).
AR# 43058
Date Created 07/08/2011
Last Updated 12/15/2012
Status Active
Type General Article
  • Ethernet 1000BASE-X PCS/PMA or SGMII