The simulation test bench provided with the Appnote is essentially a zero-length JTAG chain with example instructions to verify operation.When using an actual ACE file for simulation, especiallywhen programming a PROM, the simulation can become very slow giving the impression that the Player has stopped.If you monitor the "num_bits" register, you will typically see it counting down, but from a very large number, and the Player is just waiting for this value to reach zero.
This issue is caused by normal JTAG operations that simulate very slowly.For example, when erasing a PROM, the JTAG operation might require await time in the RUNTEST IDLE stateof60 or more seconds. This wait time is not required for simulation, so you can speed this operation up by searching in the SVF file for the all the RUNTEST operations and replacing the large wait time value.For example,thefollowing statement in the SVFfile for the erase operation might be"RUNTEST 60000000 TCK;" and you can replace it with "RUNTEST 00000007 TCK;"
After changing your SVF, run SVF2ACE again to make a new ACE file for your simulation.
Note:This is for simulation only. In your actual design, you should NOT modify your SVF file in this manner.
Forrelated issues with simulation of XAPP424, please see Xilinx Answer 24797.