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AR# 43078

Spartan-3A DSP - Why does the User Guide list AREG1 and BREG1 as the default registers?

Description

The XtremeDSP DSP48A for Spartan-3A DSP FPGAs, UG431, documents that the AREG1 and BREG1 registers are the default registers when only one input register is selected.

Solution

This is because for the Spartan-3A DSP, the AREG1 and BREG1 registers are faster than the AREG0 and BREG0 registers. This differs from Virtex devices, where the AREG0/BREG0 and AREG1/BREG1 registers are the same speed.

To improve timing, it is recommended that you use the AREG1 and BREG1 registers when only one input register is needed, and that is why the defaults are to set the AREG1 and BREG1 to 1.

AR# 43078
Date Created 07/11/2011
Last Updated 05/23/2014
Status Archive
Type General Article
Devices
  • Spartan-3A DSP