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AR# 43099

MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3

Description

The MIG 7 Series Release Notes and Known Issues have been combined into a single answer record for ease of viewing.  Please visit (Xilinx Answer 45195).

This Release Note and Known Issues Answer Record is for the Memory Interface Generator (MIG) 7 Series 1.3 released in ISE Design Suite 13.3 and contains the following information:

  • General Information
  • Software Requirements
  • New Features
  • Resolved Issues
  • Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see the IP Release Notes Guide (XTP025).

Solution

General Information

For a list of supported memory interfaces and features for 7 Series FPGAs, see:

For a list of supported frequencies for 7 Series FPGAs Memory Interfaces, see the appropriate DC and Switching Characteristics Data Sheet available in the 7 Series Documentation Center.

The MIG tool includes the appropriate frequency range for each specific memory interface configuration.

For information regarding MIG cores for other FPGAs, see the IP Release Notes Guide (XTP025) to locate the appropriate MIG Release Notes and Known Issues Answer Record.

For general design and troubleshooting information on MIG, see:

Software Requirements

  • ISE Design Suite 13.3
  • 32-bit Windows XP
  • 32-bit Linux Red Hat Enterprise 4.0
  • 64-bit/32-bit Linux Red Hat Enterprise 4.0
  • 64-bit XP professional
  • 32-bit Vista business
  • 64-bit SUSE 10
  • 64-bit/32-bit Linux Red Hat Enterprise 5.0 support
  • 64-bit Windows Vista support
  • 32-bit SUSE 10 support

New Features

  • ISE Design Suite 13.3 software support
  • Support of 8 controllers with a combination of DDR3 SDRAM, QDRII+ SRAM or RLDRAM II
  • Support of Fixed Pin Out Selection feature for RLDRAM II designs.
  • Support of Verify Pin Changes and Update Design feature for RLDRAM II designs.
  • Support of "Debug Signals Control" option.
  • VRN/VRP pins of HP banks (or) Top and bottom most pins of HR banks are used as normal I/Os for RESET_N, CKE and ODT pin allocation of DDR3 SDRAM designs

Resolved Issues

  • (Xilinx Answer 43460) MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - PHY module names changed to reflect memory type
  • (Xilinx Answer 42725) MIG 7 Series v1.2 - No CC pair available for System Clock
    • CR 613130
  • (Xilinx Answer 42726) MIG 7 Series v1.1-v1.2 QDRII+ - Model name is incorrect in sim.do for Cypress x36 component
    • CR 612249
  • (Xilinx Answer 42729) MIG 7 Series v1.1-v1.2 QDRII+ - custom x36 memory part showing the wrong data width
    • CR 613419
  • (Xilinx Answer 42730) MIG 7 Series v1.1-v1.2 QDRII+ - %CLK_STABLE is passed to CLK_STABLE parameter in .veo
    • CR 613405
  • (Xilinx Answer 44527) MIG 7 Series v1.2 DDR3 - Minimum Vccint of 1.0V requirement to achieve 1600 Mbps performance
  • (Xilinx Answer 42836) MIG 7 Series v1.2 - Incorrect Phaser IN and PHASER OUT constraints generated for compatible Artix-7 device
  • (Xilinx Answer 42811) MIG 7 Series v1.2 - Setup error on PHY Hard blocks due to incorrect timing model
  • (Xilinx Answer 42808) MIG 7 Series v1.2 - Component Switching Limit Error on PHY Hard blocks due to incorrect timing model.
  • (Xilinx Answer 43250) MIG 7 Series v1.1-v1.2 DDR3/DDR2 - Internal VREF constraint is not applied across all memory banks
  • (Xilinx Answer 42834) MIG 7 Series v1.2 DDR3 - tIH and tIS violation on CKE and ODT pins for DDR3 SDRAM designs during simulation
  • (Xilinx Answer 41981) MIG 7 Series v1.1-v1.2 DDR3 SDRAM - Addr/Ctrl pins should be limited to a single bank
  • (Xilinx Answer 42559) MIG 7 Series v1.1-v1.2 DDR3 SDRAM - additional hard block constraints are incorrectly generated when the reset_n pin is moved to a different bank for a multi-controller design.
  • (Xilinx Answer 42036) MIG 7 Series v1.1-v1.2 DDR3 - Internal/External VREF Guidelines
  • MIG Tool - Fixed issue with Internal VREF syntax as generating the UCF constraint for all selected banks
    • CR 618031
  • Fixed issues with extra UCF constraints generation for DDR3 SDRAM when ddr3_reset_n pin is allocated in a separate bank
    • CR 612761

Known Issues

  • (Xilinx Answer 42678) 13.2 -13.3 BitGen - Incorrect occurrence of "ERROR:Bitgen:342 - This design contains pins which are not constrained (LOC) to a specific location or have an undefined I/O Standard (IOSTANDARD)"
  • (Xilinx Answer 43100) MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Status signal names have changed to provide uniformity across all interfaces
  • (Xilinx Answer 43481) MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Verify UCF fails with new bank selection rules
  • (Xilinx Answer 44018) MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Synplify Pro will not be supported in 13.3
  • (Xilinx Answer 42831) MIG 7 Series v1.2-v1.3 DDR3/QDRII+/RLDRAM II - Design fails in core generation with single-ended system clock
  • (Xilinx Answer 44348) MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Not Able to Proceed Past Bank Selection or System Pins Selection Page
  • (Xilinx Answer 44350) MIG 7 Series v1.3 - Does not support -2L speed grade
  • (Xilinx Answer 44352) MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Incorrect Pinout Generated in the "Verify Pin Changes and Update Design" Flow
  • (Xilinx Answer 44356) MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Truncation issue in the system clock period calculation
  • (Xilinx Answer 44695) MIG 7 Series v1.3 - sys_rst is not validated properly using the "Verify Pin Changes and Update Design" flow
DDR3 SDRAM Known Issues
  • (Xilinx Answer 44540) MIG 7 Series v1.3 DDR3 - The example design does not generate any traffic in hardware when the Debug feature is enabled
  • (Xilinx Answer 44652) MIG 7 Series v1.3 DDR3 - Timing errors on PHYCTLEMPTY path occur at highest supported frequencies
  • (Xilinx Answer 44019) MIG 7 Series v1.2-v1.3 DDR3 - SIM_BYPASS_INIT_CAL = "OFF" is supported for hardware only and not behavioral simulation
  • (Xilinx Answer 43908) MIG 7 Series v1.2-v1.3 DDR3 - SIM_BYPASS_INIT_CAL = "SIM_INIT_CAL_FULL" option is not documented in UG586
  • (Xilinx Answer 42833) MIG 7 Series v1.2-1.3 DDR3 - Parity error for RDIMM designs during memory initialization and calibration process
  • (Xilinx Answer 42832) MIG 7 Series v1.2-1.3 DDR3 - FULL calibration mode violates tREFI requirement
  • (Xilinx Answer 44529) MIG 7 Series v1.2 DDR3 - Incorrect MAP parameters when CKE and ODT are allocated to a byte group separate from the remaining address/control signals (ERROR:Route:471)
  • (Xilinx Answer 44759) MIG 7 Series v1.3 DDR3 - No traffic is generated in hardware when DEBUG is enabled
  • (Xilinx Answer 44854) MIG 7 Series v1.3 DDR3 - Certain Configurations Cause Design to Stick in Calibration
  • TRCE timing is not guaranteed for all configurations at high frequencies. This will be fixed in MIG v1.4 to be released with ISE 13.4.

RLDRAM II Known Issues

  • (Xilinx Answer 44341) MIG 7 Series v1.3 RLDRAM II - MAP Parameters and UCF Constraints are Incorrectly Generated and Cause Implementation Failures
Revision History:
11/7/2011 - Added Known Issue Answer Record 44854

Linked Answer Records

Child Answer Records

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
44854 MIG 7 Series v1.3 DDR3 - Certain configurations cause designs to fail calibration in simulation N/A N/A
44540 MIG 7 Series v1.3 DDR3 - Example Design Does Not Generate any Traffic in Hardware with Debug Feature Enabled N/A N/A
44527 MIG 7 Series v1.2 DDR3 - Minimum Vccint of 1.0V requirement to achieve 1600 Mbps performance N/A N/A
44356 MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Truncation issue in the system clock period calculation N/A N/A
44348 MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Not Able to Proceed Past Bank Selection or System Pins Selection Page N/A N/A
44341 MIG 7 Series v1.3 RLDRAM II - MAP Parameters and UCF Constraints are Incorrectly Generated and Cause Implementation Failures N/A N/A
44019 MIG 7 Series v1.2 DDR3 - SIM_BYPASS_INIT_CAL = "OFF" is supported for hardware only and not behavioral simulation N/A N/A
44018 MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Synplify Pro not supported in 13.3 N/A N/A
43908 MIG 7 Series v1.2 DDR3 - SIM_BYPASS_INIT_CAL options Not Documented in UG586 N/A N/A
43460 MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - PHY module names changed to reflect memory type N/A N/A
42725 MIG 7 Series v1.2 - No CC pair available for System Clock N/A N/A
42726 MIG 7 Series v1.1-v1.2 QDRII+ - Model name is incorrect in sim.do for Cypress x36 component N/A N/A
42729 MIG 7 Series v1.1-v1.2 QDRII+ - custom x36 memory part showing the wrong data width N/A N/A
42730 MIG 7 Series v1.1-v1.2 QDRII+ - %CLK_STABLE is passed to CLK_STABLE parameter in .veo instantiation file N/A N/A
42832 MIG 7 Series v1.2-v1.4 DDR3 - FULL calibration mode violates tREFI requirement N/A N/A
42599 PlanAhead - What is the best method to remove ChipScope blocks and nets from the design within PlanAhead? N/A N/A
44350 MIG 7 Series v1.3 - Does not support -2L speed grade N/A N/A
42831 MIG 7 Series DDR3/QDRII+/RLDRAM II - Design Fails in Core Generation with Single-ended System Clock N/A N/A
AR# 43099
Date Created 10/13/2011
Last Updated 08/11/2014
Status Active
Type Release Notes
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG
  • MIG 7 Series