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AR# 43100 MIG 7 Series v1.3 DDR3/QDRII+/RLDRAM II - Status signal names have changed to provide uniformity across all interfaces

Description

Starting with the 13.3 software release, MIG 7 Series v1.3 uses different names for the status signals than previous versions to create uniform status signal names across all interfaces and to ease use for multi-controller designs.

Solution

For DDR3 SDRAMthe following has been changed:

  • Port "error" changed to "tg_compare_error".

For QDRII+ and RLDRAM IIdesigns the following has been changed:

  • Port "compare_error" changed to "tg_compare_error".
  • Port "cal_done" changed to "init_calib_complete".

These changes will be reflected in example_top, sim_tb_top, and the user design top modules generated by MIG.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A

Associated Answer Records

Answer Number Answer Title Version Found Version Resolved
43099 MIG 7 Series v1.3 - Release Notes and Known Issues for ISE Design Suite 13.3 N/A N/A

Actions

AR# 43100
Date Created 02/14/2012
Last Updated 05/20/2012
Status Active
Type Known Issues
Devices
  • Artix-7
  • Kintex-7
  • Virtex-7
  • Virtex-7 HT
IP
  • MIG
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